A semiconductor device such as an integrated circuit chip is produced by a sequence of hundreds of process steps. Many of them require a lithographic mask through which a pattern is imprinted on a photoresist layer. The design of such lithographic masks nowadays involves the prediction of the printed pattern taking into account optical, resist and etch phenomena, which occur at the scale of the mask features and below. These effects cause unavoidable deviations on the printed pattern with respect to the design intent. So-called “Optical Proximity Correction” (OPC) and “Electronic Design Automation” (EDA) is used for determining and making corrections to the intended initial mask design to give the best possible approximation of the design intent on the printed wafer. OPC optimization is based on the fragmentation of the initial design edges to compensate for the given phenomena, and relies on an accurate modelling to predict simulated contours of the printed features. The review of the OPC-based solution is conducted by outputting a simulated “process window” (PW) of many features. A PW defines the printability performance limits in terms of the focus and dose settings of a lithographic printing tool, within which limits a reliable print of the pattern is obtainable. Some patterns can have bigger PW than other patterns, due to various reasons such as design geometry, accuracy of the OPC modelling, and more.
Primarily for the patterns showing the smallest PW, the simulated PW are subsequently verified experimentally by manufacturing the mask and using it to print the pattern on a plurality of die areas of a photosensitive resist layer. Each die area is being printed with varying values of the focus and dose conditions. The experimental PW are determined by measuring features on the plurality of die areas. Differences between the experimental and simulated PW are evaluated and may necessitate further OPC-based optimization of the mask design.
Different measurement techniques are known for analyzing the printed dies. CD-SEM (Critical Dimension-Scanning Electron Microscope) is used to measure the Critical Dimension (CD) of a number of pattern features on the printed dies. Because of the characteristics of the measurement technique, only specific feature types can be measured, such as regular line/space widths and distances between opposite line ends. This means that the features that are most critical, according to the OPC model, and presenting the most complex geometry can often not be measured. This is particularly true considering logic structures, which have complex 2D geometries and are not regularly distributed. The PW obtained in this way does not look at the most likely positions to fail (near corners, specific line-ends, etc.). Also this technique measures only a handful of positions since measurement boxes need to be placed manually. Another technique is known as PWQ (Process Window Quantification), wherein all dies are scanned with an optical microscope to detect differences with respect to a reference die. Defects (deviations from the reference) can then be reviewed by a dedicated SEM tool. The main drawback here is the resolution, limited by the optical microscope technique, that does not allow a retrieval of meaningful quantitative data when compared to the CD-SEM technique. As OPC modelling is nowadays being tuned down to the nm-level, this is not accurate enough to assess the model and OPC quality.
As the dimensions of printed features decrease with the evolution towards sub 32 nm nodes in semiconductor processing, the criticality of the above-described design and inspection processes becomes ever greater.